1. Field of the Invention
The present invention relates to a signaling data receiving and processing unit provided in a broadband Integrated Services Digital Network (ISDN), and in particular, the present invention relates to a signaling data receiving and processing unit provided in a digital exchange in a broadband ISDN under circumstances that the digital exchange is connected with terminal equipment or adapters operating in a narrow band ISDN included in a data transfer system with the broadband ISDN.
At the present time, a switching network operating under an Asynchronous Transfer Mode (ATM) is intended to be used in a broadband ISDN. Because, the ATM switching network is expected to be most powerful for realizing the broadband ISDN. When the ATM switching network is used, a datum is transferred in the form of a cell having a fixed length. If the length of the datum is longer than the fixed length, the datum is divided into a plurality of divided data and transferred in a unit of a plurality of cells each including a divided datum having the fixed length. However, though the ATM switching network is provided in the broadband ISDN, there are cases where the ATM switching network is connected with terminal equipment and/or terminal adapters (TE/TA) each operating in a narrow band ISDN.
In narrow band ISDN, a datum is transferred under a signaling system such as Common Channel Signaling System (CCS) No. 7 or Link Access Procedure on the D-channel (LAPD) as provided or specified by CCITT. In accordance with such a signaling system, a signaling datum is transferred in a form of a frame having a variable length (not fixed length) including a Cyclic Redundancy Check (CRC) code placed at the end of the frame.
Therefore, as far as the ATM switching network is provided in the broadband ISDN in connection with TE/TA operating in the narrow band ISDN, the signaling data receiving and processing unit provided in the ATM switching network must support the signaling datum transferred from TE/TA under the signaling system used in the narrow band ISDN.
2. Description of the Related Art
FIG. 1 shows a typical format, which was provided or specified in 1989 by CCITT, for a cell used for transferring a signaling datum in the broadband ISDN. The cell consists of a header part, which will be simply called a "header" hereinafter, composed of 5 bytes and a payload part, which will be simply called a "payload" hereinafter, composed of 48 bytes. In the payload, there are adaptation control fields I and II each composed of 2 bytes and a signaling data field composed of the rest, 44 bytes, which is fixed in length. When the signaling datum is longer than the fixed 44 bytes, the signaling datum is divided into a plurality of divided signaling data sets in a plurality of cells respectively.
The header includes information called "VPI/VCI (Virtual Path Identifier and Virtual Channel Identifier)" informing or indicating "from which TE/TA the signaling datum comes". The adaptation control fields I includes information called "ST (Segment Type)" informing or indicating "to which cell the signaling datum belongs, a head cell, a middle cell, a last cell or a single cell". When the signaling datum has a length shorter than the 44 bytes, ST informs that the signaling datum belongs to or resides in a single cell. When the length is longer than 44 bytes and divided into two divided signaling data, ST in the first cell informs or indicates that the divided signaling datum belongs to a head cell and ST in the second cell informs or indicates that the divided signaling datum belongs to a last cell. When the signaling datum is divided into more than three divided signaling data, STs inform or indicate that the divided signaling data in the cells belong to a head cell, a middle cell or middle cells and a last cell respectively. The adaptation control fields II includes information called "LEN (Length)" informing or indicating "how many bytes are in the signaling data field".
Since the broadband ISDN is one of the new communication networks, a signaling data receiving and processing unit has not been developed as the prior art in the broadband ISDN. Therefore, a signaling data receiving and processing unit of the related art will be explained with respect to an analogy with a signaling system such as CCS No. 7 or LAPD in narrow band ISDN.
The operation of a signaling data receiving and processing unit of the related art will be explained in reference to FIGS. 2, 3, 4 and 5. FIG. 2 is a block diagram of a signaling data receiving and processing unit (SIG DATA R/P) 100 of the related art; FIG. 3 is a time chart for explaining the function of the block diagram in FIG. 2; FIG. 4 is an example of a stored state of data in a data memory (DM) 2 in SIG DATA R/P 100 in FIG. 2; and FIG. 5 is an example of a stored state of data in a control memory (CM) 4 in SIG DATA R/P 100 in FIG. 2. In FIGS. 3, 4 and 5, the same symbols as in FIG. 2 are used.
As shown in FIG. 2, SIG DATA R/P 100 belongs to a digital exchange (DEX) 300 including a well known central controller (CC) 200 and consists of a receiving block (R-BLOCK) 101 and an analyzing block (A-BLOCK) 102. The cells each including the divided signaling datum are sent from TE/TA (however, only TE will be discussed for simplicity hereinafter) to R-BLOCK 101 and stored in DM 2. The divided signaling data stored in DM 2 are read into A-BLOCK 102 and combined into a frame of the signaling datum therein. The signaling datum formed in the frame thus will be called the original signaling datum hereinafter. In A-BLOCK 102, the original signaling datum is analyzed and the analyzed result is sent to CC 200.
When the number of TE devices is "M+1" in the data transfer system and at least "n" is provided as the number of addresses for each TE in DM 2, DM 2 has memory regions for storing the divided signaling data as shown in FIG. 4, and CM 4 for controlling DM 2 has memory regions for storing control signals as shown in FIG. 5. In FIG. 5, two memory regions are provided for each VPI/VCI, corresponding to "DM start address (add)" and "DM work add" respectively for continuously storing the divided signaling data for each TE, in DM 2. That is, "DM start add" is an address used for starting to store the original signaling datum in DM 2 and "DM work add" is an address used for storing the divided signaling data into DM 2.
When cells are sent to SIG DATA R/P 100, the cells are usually sent from a TE at intervals so that other cells are sent from other TEs in between the intervals. However, in FIG. 3, the operation of SIG DATA R/P 100 is explained in a case where the cells are sent from the TE to SIG DATA R/P 100 successively without having the intervals, for purposes of simplifying the explanation. Furthermore in FIG. 3, the original signaling datum is divided into two divided signaling data, a first divided signaling datum composed of 44 bytes and a second divided signaling datum composed of 12 bytes, transferred in a unit of two cells, a first and a second cell, respectively.
When SIG DATA R/P 100 receives the first and second cells as shown in FIG. 3(a), VPI/VCIs in the first and second cells are latched or stored by a first VPI/VCI latch (VPI/VCI-L1) 61 and second VPI/VCI latches (VPI/VCI-L2) 62 arranged in series, producing a latched signal "M" respectively as shown in FIGS. 3(c) and 3(d). The output from VPI/VCI-L2 62 is sent to both a TE/TA discriminator (TE/TA DISC) 56 in A-BLOCK 102 and a control memory address generator (CM Add GEN) 5 in R-BLOCK 101. The function of TE/TA DISC 56 will be explained later. The CM Add GEN 5 is for generating control memory addresses (CM Add) to be used in CM 4. Since CM 4 is provided to store two addresses for each TE as explained in reference to FIG. 5 and "M" is input to CM Add GEN 5, CM Add GEN 5 generates two CM addresses, "2M" including "DM start Add" and "2M+1" including "DM work Add", and outputs them as shown in FIG. 3(f).
The STs in the first and second cells are latched by an S/T latch (S/T-L) 7, producing signals informing "head cell" and "last cell" for the first and second cells respectively as shown in FIG. 3(b). The LENs in the first and second cells are latched by an LEN latch (LEN-L) 8, producing signals informing "44" and "12" for the first and second cells respectively as shown in FIG. 3(e). The outputs from ST-L 7 and LEN-L 8 are sent to a data memory address recognizer (DM Add RECOG) 53 in A-BLOCK 102 as shown in FIG. 2. The function of DM Add RECOG 53 will be explained later. In the case of the first cell, when CM 4 receives CM address "2M+1" from CM Add GEN 5 at an address input terminal (Add) of CM 4, an arbitrary datum "A", which has been obtained in CM 4 when CM 4 was initialized, is output from a data output terminal (Dout) of CM 4 as shown in FIG. 3(g). The "A" output from CM 4 is sent to a data memory address counter (DM Add CNT) 3 and DM Add RECOG 53 respectively. When "A" is loaded into DM Add CNT 3, counting is advanced therein step by step as shown by "A", "A+1", "A+2", - - - , "A+43" in FIG. 3(h). During the counting, the 44-byte first divided signaling datum is written into DM 2 through a data input terminal (Din) of DM 2 in the order of "A", "A+1", "A+2", - - - , "A+43" as shown by a time interval marked "the first" in FIG. 3(i).
In the case of the second cell, the same operation as in the first cell is performed. However, CM 4 or resets the output "A" to "A+44" as shown in FIG. 3(g). This is for preventing the second divided signaling datum from erasing the first divided signaling datum stored in DM 2, when the second divided signaling datum is stored in DM 2. The renewal is performed in CM 4 at a time (a) shown in FIG. 3(k) by sending CM address "2M+1" from CM Add GEN 5 to CM 4 and feeding the output of DM Add CNT 3 back to Din of CM 4, as shown in FIG. 2. The second divided signaling datum is stored in DM 2 in the order of "A+44", "A+45", - - - and "A+87" as shown by a time interval marked "the second" in FIG. 3(i).
In the same way as renewing or updating the CM output at the time (a), in case of the second cell, the CM output is renewed or updated at a time (c) in FIG. 3. However, renewal for "DM start Add" must be performed at a time (d) before the time (c) as shown in FIG. 3(j). This is for preparing the next frame of the signaling datum. That is, if there were no renewal or update for "DM start Add" at the time (d), A-BLOCK 102 would read the signaling data of two frames when A-BLOCK 102 is triggered to analyze the signaling datum in the next frame.
After the second divided signaling datum is stored in DM 2, A-block 102 is triggered at a time (b) shown in FIG. 3(1), so as to start the analysis of the signaling datum.
As mentioned before, the outputs from ST-L 7, LEN-L 8, CM 4 and DM Add CNT 3 are sent to DM Add RECOG 53. Therefore, at the time (b), DM Add RECOG 53 recognizes the outputs from ST-L 7, LEN-L 8, CM 4 and DM Add CONT 3. Since the output from VPI/VCI-L2 62 is sent to TE/TA DISC 56, TE/TA DISC 56 discriminates TE and sends the discrimination result to a data analyzer (DATA ANA) 52 in A-BLOCK 102. Therefore, DATA ANA 52 starts to analyze the original signaling datum at the time (b). The recognition result from DM Add RECOG 53 is sent to a data address generator (DM Add GEN) 51 in A-BLOCK 102. The DM Add GEN 51 generates addresses for reading the first and second divided signaling data stored in DM 2 and applies them to DM 2 through Add of DM 2. Then, the first and second divided signaling data are read out from Dout of DM 2 to DATA ANA 52. In DATA ANA 52, information necessary to control DEX 300 is analyzed using the original signaling datum obtained by combining the divided signaling data read from DM 2 and the result is sent to CC 200. The analysis is performed during an interval shown in FIG. 3(m).
The DM Add RECOG 53 also outputs a signal necessary to trigger a CRC check timing generator (CRC TIMING GEN) 55 in A-BLOCK 102, then CRC TIMING GEN 55 produces a timing signal to perform the CRC check. Meanwhile, the CRC check is performed in a CRC checker (CRC CHK) 9. In CRC CHK 9, the well known CRC counting in performed by counting bits of the first and second divided signaling data and performing a matching operation between the counted result and the CRC code placed at the end byte of the original signaling datum, in other words, at the end byte of the second divided signaling datum in the last cell. The original signaling datum and the CRC code are sent from Dout of DM 2 as shown in FIG. 2 and the matching is performed by the timing signal from CRC TIMING GEN 55 at a time marked (e) in FIG. 3(n). The CRC check result from CRC CHK 9 is sent to an analysis judging unit (ANA JUDGE) 54 in A-BLOCK 102, for judging or determining whether the analysis is advanced. The judged result is sent to DATA ANA 52. If the result is no good (NG), DATA ANA 52 stops the analysis of the original signaling datum and also stops sending the analyzed result to CC 200.
Problems in the Related Art
The SIG DATA R/P 100 of the related art has two problems. The first problem is that DM 2 must have too many memory regions. The second problem is that the timing for obtaining the CRC check result is too late. Because the CRC matching is performed at the last byte of the signaling datum read from DM 2. Therefore, when the analysis is stopped due to the NG result of the CRC matching, the analysis is almost completed in A-BLOCK 102, which means time for analyzing the read signaling datum is substantially all wasted.
The first problem will be explained further by using an example. In the header of the cell, 3 bytes are provided for VPI/VCI. Therefore, if at least 500 addresses are required as the address number "n" for each TE in DM 2 (see FIG. 4), the following addresses are required in DM 2:
500 address X 16M (mega)=8 G (giga) address. PA1 500 address.times.1,000=500K address.
However, it is known at the present time that the number of TEs used is almost one thousand. In other words, the following addresses are enough for DM 2:
Therefore, the memory regions come to naught or are not used in DM 2.